The present disclosure generally relates to the field of electronics. More particularly, some embodiments of the invention relate to die backside metallization (DBM) and surface activated bonding (SAB) for stacked die packages.
A computer system generally includes various components that may communicate with each other during operation of the computer system. Sometimes these components may be located on different dies. Hence, communication speed of the various dies may be paramount to the performance achieved by a computer system.
In some current computer systems, dies may interlink via relatively long traces, for example, through a computer system motherboard and various substrate levels. Long vertical paths may minimize the extension of current motherboard system architecture, introduce signal propagation delay, or generate additional heat. Some current computer systems aim to reduce the length of interlinks between various dies by stacked die technology and direct silicon via technology for direct die interlink. Utilization of direct silicon via technology for stacked dies may, however, require one die to carry the power source for another die. This approach may generate thermal stress on the die that is responsible for carrying the power source. Also, one of the two dies in a stacked die design may receive minimal input/output (I/O) relative to the remaining die.